An Efficient Implementation of Built in Self Diagnosis for Low Power Test Pattern Generator
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Keywords
Logic Built In Self-Test (BIST), Fault diagnosis, Bit Swapping-Linear Feedback Shift Register(BS-LFSR), Data Encryption Standard (DES), Test Pattern Generation.
Abstract
A New architecture of Built-In Self-Diagnosis is presented in this project. The logic Built-In-Self-Test architecture method is extreme response compaction architecture. This architecture first time enables an autonomous on-chip evaluation of test responses with negligible hardware overhead. Architecture advantage is all data, which is relevant for a subsequent diagnosis, is gathered during just one test session. Due to some reasons, the existing method Built-In Self-Test is less often applied to random logic than to embedded memories.
The generation of deterministic test patterns can become prohibitively high due to hardware overhead. The diagnostic resolution of compacted test responses is in many cases poor and the overhead required for an acceptable resolution may become too high. Modifications in Linear Feedback Shift Register to generate test pattern with security for modified Built-In-Self-Test applications with reduced power requirement. The modified Built-In-Self-Test circuit incorporates a fault syndrome compression scheme and improves the circuit speed with reduction of time.
The generation of deterministic test patterns can become prohibitively high due to hardware overhead. The diagnostic resolution of compacted test responses is in many cases poor and the overhead required for an acceptable resolution may become too high. Modifications in Linear Feedback Shift Register to generate test pattern with security for modified Built-In-Self-Test applications with reduced power requirement. The modified Built-In-Self-Test circuit incorporates a fault syndrome compression scheme and improves the circuit speed with reduction of time.
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References
1. Baloji Naik.B, Dr.V.Venkata Rao,(2012)“Peak- and Average-Power Reduction in Check-Based BIST by using Bit-Swapping LFSR and Check-Chain Ordering” IOSR Journal of Computer Engineering,ISSN: 2278-0661 Volume 4, Issue 4, PP 36-42.
2. Bala Souri.K, K.Hima Bindu, K.V. Ramana Rao (2011)“A Built-In Self-Repair Scheme for Random Access Memories with 2-D Redundancy”. International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-1, Issue-5.
3. Chiraz Khedhiri1, Mouna Karmani1 and Belgacem Hamdi(2011) “A BIST Generator CAD Tool for Numeric Integrated Circuits” International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.2.
4. Chethan J, Manjunath Lakkannavar(2013) “Design of Low Power Test Pattern Generator using Low Transition LFSR for high Fault Coverage Analysis” I.J. Information Engineering and Electronic Business, , 2, pp-15-21.
5. Divya.E1, Prof.S.Arumugam(2013) “High Speed and Low Power implementation of 3-Weight Pattern Generation Based on Accumulator” International Journal of Advanced Research in Computer and Communication Engineering Vol. 2, Issue 2.
6. Lubna Naim, Tarana A. Chandel,(2014 ) “Design of Low Transition Pseudo-Random Pattern Generator for BIST Applications”International Journal of Computer Application(0975-8887)Volume 87-No. 1.
7. Praveen Kumar Aggarwal, Vandana Yadav, Dr. Arti Noor, “DFT (Design for Testability) Pattern Generation Task for Circuit Under Test” International Journal of Engineering Research and Applications Vol. 1, Issue 2, pp.190-193.
8. Praveen J M N Shanmukhaswamy (2012) “ Power Reduction Technique in LFSR using Modified Control Logic for VLSI Circuit” Special Issue of International Journal of Computer Applications (0975 – 8887) International Conference on Electronic Design and Signal Processing.
9. Ramakrishna Porandla, Gella Ravikanth, Podili Ramu (2013) “Power Optimization In Digital Circuits Using Scan-Based BIST” International Journal of Research in Computer an Communication Technology, Vol 2, Issue 6,
10. Rani Varghese ,V.Magudeeswaran,(2014) “VLSI Implementation of Test Pattern Generator for Built in self Test”, I J I P A:ISSN 0975-8178,pp.61-65.
2. Bala Souri.K, K.Hima Bindu, K.V. Ramana Rao (2011)“A Built-In Self-Repair Scheme for Random Access Memories with 2-D Redundancy”. International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-1, Issue-5.
3. Chiraz Khedhiri1, Mouna Karmani1 and Belgacem Hamdi(2011) “A BIST Generator CAD Tool for Numeric Integrated Circuits” International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.2.
4. Chethan J, Manjunath Lakkannavar(2013) “Design of Low Power Test Pattern Generator using Low Transition LFSR for high Fault Coverage Analysis” I.J. Information Engineering and Electronic Business, , 2, pp-15-21.
5. Divya.E1, Prof.S.Arumugam(2013) “High Speed and Low Power implementation of 3-Weight Pattern Generation Based on Accumulator” International Journal of Advanced Research in Computer and Communication Engineering Vol. 2, Issue 2.
6. Lubna Naim, Tarana A. Chandel,(2014 ) “Design of Low Transition Pseudo-Random Pattern Generator for BIST Applications”International Journal of Computer Application(0975-8887)Volume 87-No. 1.
7. Praveen Kumar Aggarwal, Vandana Yadav, Dr. Arti Noor, “DFT (Design for Testability) Pattern Generation Task for Circuit Under Test” International Journal of Engineering Research and Applications Vol. 1, Issue 2, pp.190-193.
8. Praveen J M N Shanmukhaswamy (2012) “ Power Reduction Technique in LFSR using Modified Control Logic for VLSI Circuit” Special Issue of International Journal of Computer Applications (0975 – 8887) International Conference on Electronic Design and Signal Processing.
9. Ramakrishna Porandla, Gella Ravikanth, Podili Ramu (2013) “Power Optimization In Digital Circuits Using Scan-Based BIST” International Journal of Research in Computer an Communication Technology, Vol 2, Issue 6,
10. Rani Varghese ,V.Magudeeswaran,(2014) “VLSI Implementation of Test Pattern Generator for Built in self Test”, I J I P A:ISSN 0975-8178,pp.61-65.
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Published
Sep 27, 2015
Article Details
How to Cite
Nithya, N. (2015). An Efficient Implementation of Built in Self Diagnosis for Low Power Test Pattern Generator. International Journal of Students’ Research in Technology & Management, 3(2), 269-272. Retrieved from http://giapjournals.com/index.php/ijsrtm/article/view/152
Section
Electronics Engineering
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